APFC Panel Step Size Selection Procedure

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APFC Panel Step Size Selection Procedure
APFC Panel Step Size Selection Procedure

The selection of step size and the number of capacitor steps is one of the most important aspects in the design of Automatic Power Factor Correction (APFC) panels. 

Proper selection directly impacts 

  • Power factor correction accuracy, 
  • System stability, 
  • Equipment life and 
  • Overall panel cost.

An optimized design ensures an efficient reactive power compensation while minimizing switching stress & investment cost.

The maximum capacitor step size depends on 

  • Load variation, 
  • Current transients and 
  • Voltage transients.

Large load variations need larger capacitor steps.

Switching large capacitors (>100 kVAr) produces high inrush current up to 75 kA.

Large switching may cause voltage transients affecting sensitive equipment.

Recommendation

Maximum step size must be 100 kVAr.

Use capacitor duty contactors (or) thyristor switching modules.

Practically, utilize 2 x 50 kVAr banks in parallel for a 100 kVAr step.

APFC Maximum Step Size Selection
APFC Maximum Step Size Selection

Minimum step size determines accuracy of power factor (PF) correction.

APFC relay sensitivity ~2.5%.

Electricity boards consider power factor (PF)  up to 0.99.

Ideal power factor (PF) range: 0.96 to 0.99.

Thumb Rule

Minimum step size = 5% to 10% of total kVAr.

Panel SizeMinimum Step
Up to 100 kVAr5 kVAr
100–500 kVAr10–25 kVAr
500–1000 kVAr25 kVAr

Number of steps in APFC panels depends on controller technology and cost.

Conventional controllers need more steps.

Intelligent controllers allow for mixed step sizes and fewer steps.

Design Objectives

• Maximum electrical combinations.

• Minimum physical steps.

The number of steps must balance:

  • Accuracy
  • Cost
  • Panel size

Conventional Controllers

  • Need more steps
  • Follow linear (or) circular switching

Advanced Controllers (Intelligent)

  • Use optimized switching logic.
  • Allow mixed step sizes.
  • Reduce number of steps.
Steps in APFC Panels
Steps in APFC Panels

An ideal APFC panel should have:

  • Improves flexibility
  • Enhances PF correction accuracy

Reduces:

  • Panel size
  • Cost
  • Maintenance

For 100 kVAr Panel

Case A:

  • 10 steps of 10 kVAr
  • 10 physical steps
  • 10 electrical steps

Case B:

  • 50 + 25 + 15 + 5 + 5
  • 5 physical steps
  • 20 electrical steps

Here, Case B is more efficient.

For 300 kVAr Panel

Case A:

  • 25 kVAr x 12
  • 12 physical steps

Case B:

  • 100 + 3 x 50 + 2 x 25
  • 6 physical steps

Case B reduces the hardware while maintaining performance.

For 600 kVAr Panel

Case A:

  • 50 kVAr x 12
  • 12 steps

Case B:

  • 3 x 100 + 5 x 50 + 2 x 25
  • 10 physical steps
  • 24 electrical combinations

Case B provides higher resolution with fewer steps.

Large Steps (Up to 100 kVAr)

  • Used for the base load compensation

Medium Steps

  • Used for a variable load correction

Small Steps (5–10% or 25 kVAr)

  • Used for the fine tuning
APFC Panel
APFC Panel
Panel RatingStepsSuggested Combination
100 kVAr550 + 25 + 15 + 5 + 5
300 kVAr6100 + 3 x 50 + 2 x 25
600 kVAr103 x 100 + 5 x 50 + 2 x 25
1000 kVAr12Mixed (100, 50, 25 kVAr)

This table is primarily suitable for most of the industrial applications.

Final step selection should always be based on:

  • Load profile study,
  • Harmonic conditions and
  • Switching technology.
Panel Rating (kVAr)Physical Step Size (kVAr)No. of Physical StepsElectrical / Logical Steps (kVAr)No. of Electrical Steps
352×12.5 + 2×545, 10, 12.5, 17.5, 22.5, 25, 30, 358
502×12.5 + 2×10 + 1×555, 10, 12.5, 15, 17.5, 20, 22.5, 25, 27.5, 30, 35, 37.5, 40, 45, 5015
752×25 + 2×10 + 1×555, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 70, 7513
1002×25 + 2×15 + 1×555, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 95, 10013
1252×12.5 + 2×25 + 50512.5, 25, 37.5, 50, 62.5, 75, 87.5, 100, 112.5, 12510
1502×12.5 + 2×25 + 50612.5, 25, 37.5, 50, 62.5, 75, 87.5, 137.5, 15012
1752×12.5 + 2×25 + 50612.5, 25, 37.5, 50, 62.5, 75, 87.5, 162.5, 17514
2002×12.5 + 2×25 + 50612.5, 25, 37.5, 50, 62.5, 75, 87.5, 187.5, 20016
2252×12.5 + 2×25 + 50612.5, 25, 37.5, 50, 62.5, 75, 87.5, 212.5, 22518
2504×50 + 2×25625, 50, 75, 100, 125, 150, 175, 200, 225, 25010
2751×50 + 1×25625, 50, 75, 100, 125, 150, 175, 200, 225, 250, 27511
3001×100 + 3×50 + 2×25625, 50, 75, 100, 125, 150, 175, 200, 275, 30012
3501×100 + 3×50 + 4×25825, 50, 75, 100, 125, 150, 175, 200, 325, 35014
4002×100 + 2×50 + 4×25825, 50, 75, 100, 125, 150, 175, 200, 375, 40016
4502×100 + 3×50 + 2×25825, 50, 75, 100, 125, 150, 175, 200, 425, 45018
5002×100 + 4×50 + 2×25825, 50, 75, 100, 125, 150, 175, 200, 475, 50020
5503×100 + 3×50 + 2×251025, 50, 75, 100, 125, 150, 175, 200, 525, 55022
6003×100 + 5×50 + 2×251025, 50, 75, 100, 125, 150, 175, 200, 575, 60024
6504×100 + 4×50 + 2×251025, 50, 75, 100, 125, 150, 175, 200, 625, 65026
7004×100 + 5×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 675, 70028
7505×100 + 3×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 725, 75030
8005×100 + 5×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 775, 80032
8506×100 + 4×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 825, 85034
9006×100 + 5×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 875, 90036
9507×100 + 4×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 925, 95038
10008×100 + 2×50 + 2×251225, 50, 75, 100, 125, 150, 175, 200, 975, 100040
  • More steps do not always have a mean better performance
  • Intelligent controllers reduce the required steps
  • Always mix:
    • Large
    • Medium
    • Small capacitors
  • Avoid the overcompensation (leading PF)
  • Also consider harmonic conditions
  • Maximum step size must not exceed 100 kVAr
  • Minimum step size must be 5–10% of total capacity
  • Use a mixed step configuration
  • Prefer intelligent APFC controllers
  • Always analyze load profile before design

The optimum selection of capacitor step size and number of steps is essential for achieving an efficient and economical APFC panel performance.

A balanced combination of different step sizes that ensures an accurate

  • Power factor correction, 
  • Reduced switching stress and 
  • Optimized system cost.